The present invention relates to electronic semiconductor devices and methods of fabrication, and more specifically, to very large scale integrated circuits which may incorporate multiple levels of interconnect.
Interconnect and contact system technology are increasingly a focus of attention as the demands of VLSI circuit development require smaller contact dimensions and multiple levels of finely patterned electrical conductors. In particular, the use of multiple layers of interconnect has placed great demands on improving processing technology related to the etching of contact vias and the planarization of interlevel insulators to ensure adequate coverage of severe changes in device topology. In processes that continue to employ aluminum-based metal interconnect, the contact vias may be filled with a selectively deposited metal such as tungsten to reduce the contact step coverage problems that have been observed in the past. See, for example, Broadbent, E. K. et al, J. Electrochem. Soc., Vol. 131, p. 1427 (1984).
More recently, blanket chemical vapor deposited (CVD) tungsten has been investigated as an alternative interconnect metallization for VLSI application. See "Blanket CVD Tungsten Interconnect For VLSI Devices", Sunil Mehta et al, 1986 V-MIC Conf., June 9-10, pp. 418-435. As reported by the above authors, tungsten interconnect offers significant advantages over aluminum based systems. For example, tungsten affords a marked improvement in electromigration resistance. Moreover, CVD tungsten may be processed to produce a very conformal film which has greatly improved step coverage thereby minimizing the previous restraints presented by severe steps in the underlying topology. In addition, tungsten withstands higher processing temperatures than aluminum making it suitable for use in processes that employ high temperature operations (such as insulator reflow) after tungsten deposition.
A preferred deposition chemistry for low pressure chemical vapor deposition (LPCVD) of tungsten films in VLSI processes involves the hydrogen reduction of WF6. See, for example, "Low Pressure Chemical Vapor Deposition of Tungsten and Aluminum for VLSI Applications", R. A. Levy et al., Journal of Electrochemical Society, February, 1987, pp. 37C-49C. As previously reported, the reduction reaction is rate limited by the disassociation of H2 into atomic hydrogen at the reaction surface. As a result, the deposition temperature may be chosen to selectively deposit on silicon only or to deposit on both sili and insulator (for example SiO2). At temperatures below about 5 degrees C. the insulator will not catalyze the H2 disassociation but a silicon surface will. This makes possible the selective deposition of tungsten in contact vias for the purpose of providing plugs to aid in reducing severe steps for later metallization processes as mentioned previously. At higher temperatures, tungsten films will deposit on both silicon and insulator surfaces making a suitable VLSI interconnect film.
While CVD tungsten deposition using the hydrogen reduction of WF6 may be performed in such a way as to result in extremely conformal films, the resulting significant surface roughness presents a variety of problems. FIG. 1 depicts a representative cross section of a typical contact to diffusion 12 in a semiconductor substrate 10. The via formed in insulator 14 is very conformally covered by tungsten film 16 as shown by the slight deviation from surface planarity at region 19. Typical of such a conformal film are the very large surface asperities or protrusions 18. That is, the height of localized peaks of material at the surface (asperity height) is greater for deposition conditions that result in very conformal films. Similar vias in insulating layers are used on semiconductor wafers to provide alignment markers to permit automated alignment during processing. These markers may be detected by exposing the surface to a light source and detecting the reflected signal. One problem created by excessive tungsten surface roughness is the inability to pattern thick layers because a reduced signal to noise ratio prevents the detectors on the alignment device from finding the alignment markers. In addition, the etch chemistry typically used to etch the tungsten is not selective to oxide. As a result of the tungsten surface roughness, pitting of the underlying insulator (14) may result during the anisotropic etching of the tungsten film. Yet another disadvantage of the rough conformal film of FIG. 1 is that asperities 18 present points of increased electric field to an upper level conductor separated from film 16 by an overlying insulator (not shown). Finally, the recesses in the surface of film 16 may provide regions of voiding during the formation of an overlying insulator which in turn may present reliability problems.
While the CVD tungsten deposition conditions may be modified to provide smoother tungsten films with acceptable resistivity, the conformality is poor.
Accordingly, it is an object of the present invention to provide a new and improved process for forming a metallic film suitable for use as interconnect in very large scale integrated circuits. It is a further object of the invention to provide a process for forming a very conformal metallic film having reduced surface roughness. Yet another object of the invention is to provide a process for forming a conformal blanket tungsten film on the surface of an insulating layer. Still a further object of the present invention is to provide a conformal metallic film having reduced surface roughness on the surface of an insulating layer.
Still a further object of the present invention is to provide a conformal metallic film having reduced surface roughness on the surface of an insulating layer.